Staff Engineer, Digital Design Engineering

We're looking for a highly skilled Senior Digital Verification Engineer with extensive hands-on experience in SystemVerilog (SV) and UVM methodology. In this role, you'll be instrumental in developing robust verification plans, building reusable testbench components, and driving comprehensive coverage closure for complex digital blocks at various levels.

Responsibilities:

• Collaborate with cross-functional teams to meticulously review and refine architecture and design specifications.
• Develop comprehensive verification plans for complex digital modules at the IP, Subsystem, and SoC levels.
• Design and implement reusable testbench components, including drivers, monitors, and scoreboards, utilizing SV-UVM methodology.
• Work closely with design teams to achieve rigorous coverage closure.
• Coordinate with silicon test and evaluation teams to develop and deliver effective test patterns.

Required Qualifications:

• Extensive hands-on experience (6+ years) in digital verification using SystemVerilog (SV) and UVM methodology.
• Proven expertise in developing verification plans for complex digital blocks.
• Proficiency in creating testbench environments at IP and/or Subsystem levels.
• Experience in constrained random stimulus generation and coverage closure.
• Competence in Gate-Level Simulation (GLS) setup and debugging.
• Strong debugging skills and analytical problem-solving capabilities.
• Familiarity with ARM-AMBA protocols.

Advantageous Skills:

• Experience in formal verification and SystemVerilog Assertions (SV-Assertion) coding.
• Exposure to mixed-signal verification.
• Exposure to Ethernet interface standards.