Verification of mixed signal designs and sub-systems using leading edge verification methodologies.
Development of directed and constrained random test cases in System Verilog
Architect, implement, and/or manage complete metric-driven System Verilog and UVM verification environments as determined by project complexity
Define test plans, tests and verification methodology for block / chip-level verification. Work with the design team in generating test-plans and closure of code and functional coverage.
Continuous interaction with analog and digital teams in enabling top-level chip verification.
Support post-silicon verification activities of the products working with design, product evaluation, and applications engineering team.

Minimum qualifications

BSEE + 7 years or MSEE + 5 years Digital and/or Mixed Signal IC verification experience.
Strong written and verbal communication skills.
Strong coding, object-oriented programming, and documentation skills.
Strong System Verilog fluency in verification domain.
System Verilog Assertion for Dynamic and Formal Verification.
Experience in developing test benches, testcases using System Verilog and UVM
Knowledge of test-plan generation, coverage analysis, transaction level modeling, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
Knowledge of and capability to execute the entire digital verification process without significant assistance

Preferred qualifications

Staff Digital Verification Engineer