Staff Digital Design Engineer

• Translate requirements to design specification by working closely with system architects
• Translate the design specification to optimal digital micro-architecture
• RTL coding using Verilog and System Verilog
• Meet power, performance and area goals by micro-architecture optimization
• Block level Designer verification
• Work closely with DV team to develop test-plans
• Front end implementation - Lint/CDC , synthesis, Timing constraint development
• Work closely with DFT and PD teams for signoff
• Support Silicon validation
• Mentor junior design engineers

Position requirements

• BE/BS/Mtech/M.E/PhD degree in Electrical/Electronics/Computer science from a reputed institute
• 6-15 years of relevant experience
• In depth understanding of digital logic design principles - control intensive, data-path intensive and multi domain clocking
• Strong hands-on RTL coding experience and debugging skills
• Digital Subsystem, clocking and full chip integration experience
• Expertise in timing constraints development and critical path timing closure
• Very good Experience in Synthesis and LEC
• Knowledge of industry standard bus protocols such as AHB, APB, AXI
• Experience in digital signal processing and Matlab modeling is highly desirable
• Experience in Processor subsystem design is highly desirable
• Excellent verbal and written communication skills to work effectively with teams spread geographically
• Experience in mentoring junior engineers