SI

Software Engineer Advanced

Siemens
Noida6-11 LPA Posted 29 Apr 2025
FULL TIME
verification methodology manual
System Verilog
Software Testing

Job Description

 This is your role.  

  • Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques.
  • You will specify, implement, test and enhance these verification components for a wide range of end user applications.
  • You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger.
  • You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues.

 

  • We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 3-7 years of hands-on experience to the table.
  • You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc.
  • You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc.
  • We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas!

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