Senior Manager, DFT Design

• Lead and manage the DFT team responsible for delivering comprehensive DFT solutions for complex SoCs.
• Take end-to-end ownership of the DFT lifecycle - from architecture definition to silicon bring-up and production ramp.
• Collaborate cross-functionally with architecture, design, and physical design teams to ensure optimal testability integration.
• Define and track DFT milestones, quality metrics, and progress, ensuring alignment with program schedules and quality standards.
• Represent DFT in program and customer meetings, communicating status, risks, and mitigation plans.
• Architect and guide the implementation of DFT features, including Scan chain insertion and optimization, Test compression techniques, LBIST/MBIST (including repair logic), Boundary scan structures
• Lead efforts in performing DFT rule checks (DFT DRC) at RTL and netlist levels to ensure compliance with internal and industry standards.
• Use industry-standard EDA tools (e.g., Cadence, Siemens/Tessent) for DFT Design, DRC, Pattern Generation and work with EDA/Internal CAD team for tool/flow improvements
• Drive DFT pattern generation and validation, including gate-level simulations with and without SDF.
• Partner with the verification team to define and execute DFT verification plans.
• Collaborate with physical design and STA teams to implement DFT constraints and strategies for synthesis and timing closure.
• Analyze silicon test data, debug test failures, and work with the test engineering team to resolve bring-up and production issues.
• Provide technical leadership, mentorship, and career development for DFT engineers on the team.

Qualifications and Experience:

• Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.
• Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs.
• Strong team management and leadership experience with a track record of mentoring and growing engineering talent.
• Bachelors or Master s degree in Electrical/Electronics Engineering or a closely related field.
• 12+ years of hands-on experience in DFT methodologies and industry-standard test techniques.
• Deep knowledge and hands-on experience with:

Logic BIST (LBIST)

Automatic Test Pattern Generation (ATPG)

DFT Rule Checks (DFT DRC)

Scan chain compression and stitching

Low-power DFT techniques and constraints

Memory BIST (MBIST) including repair mechanisms

Boundary Scan (IEEE 1149.1)

Analog DFT strategies

JTAG architecture and TAP integration

DFT-specific STA constraints

• Proficient in using industry-standard DFT EDA tools, including cadence, Siemens.
• Strong scripting and automation skills using Perl, Tcl, and/or Python.
• Solid understanding of digital design fundamentals, including RTL design, Lint/CDC, low power checks, and the full ASIC design flow.
• Excellent problem-solving skills, with the ability to troubleshoot and resolve complex DFT issues efficiently.
• Strong communication and interpersonal skills, capable of working effectively in cross-functional and team-oriented environments.