ANAnalog Devices
Senior Engineer, Physical Design Engineering
Bangalore ₹4-8 LPA Posted 25 Jun 2025
FULL TIME
Tcl
Place And Route
Sta
floorplanning
Parasitic Extraction
Job Description
- BTech/MTech degree in Electrical/Electronic from a reputed institute with 4-8 years of experience in the field of Digital place and route
- Hands on experience with the implementation (PnR Signoff) of complex high speed SoC designs in cutting edge process technologies (22 nm, 16 nm, 7 nm, etc).
- Hands on experience in handling the tapeout of complex high speed SoC designs in cutting edge process technologies
- Floor Planning, Power Plan, Place and Route, Clock Planning and Clock Tree Synthesis, Parasitic Extraction
- Strong expertise in Static Timing analysis , constraint development and sign off.
- Innovate on the flows to meet the QoR targets and ensure predictability
- Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.
- Being proficient in TCL, Perl etc.