Senior Engineer, Digital Design Engineering

• Technology enablement and reference flow development of advance Power Signoff techniques (IR/EM analysis) for cutting edge tech nodes/Power Intent SoC designs. This needs a solid understanding of the challenges seen in deep sub-micron process nodes.
• Interfacing with EDA vendors to enable production-ready tool sets and to develop solutions to enhance PPA metrics for different designs.
• Collaborate with different SoC design teams to develop solution for advanced/cutting edge implementation and advanced process nodes.
• Engage with Vendors, PD teams and IP teams to resolve issues arising in tech enablement and Signoff (IR/EM) execution.
• Validating the developed solutions across the end-to-end Implementation domains: Pre/Post synthesis, DFT, PnR, Timing/Power signoff, and physical verification

Requirements

• Bachelor s degree in electrical/computer engineering master s degree is a plus.
• Minimum of 6 years Digital Design Implementation work experience with below requirement Experienced in Power Signoff (RTL power/IR/EM analysis) on advanced technologies
• Signoff tool experience on Cadence Voltus/Industry equivalent
• Hands on Power intent design flow is a plus
• Very good understanding on end to end implementation flow
• Understanding the usage tech lefs & std cell libraries, power tech files
• Experience in Timing closure, Early power estimation techniques, design robustness and making right PPA trade-off decisions.
• Strong problem-solving skills with excellent analytical and debugging skills.
• Deep knowledge on scripting and software languages including Python/PERL/TCL, Linux/Unix shell.
• Experience of working as part of a larger team and working towards achieving timely quality release