Senior Engineer, Design Verification Engineering

• Lead, Develop and deploy best-in-class Emulation/FPGA prototyping tools and methodologies across ADI Product Lines
• Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces
• Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future
• Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow
• Training, deployment, and support of verification methodologies within ADI

Position Requirements :

• Bachelors/master s degree in electrical/Electronics/VLSI with 4-8 years of experience
• Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred.
• Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred
• Expertised in one or more of scripting languages(shell,python,perl) is highly preferred
• Proficient in SV, UVM, integration of third party VIPS, Accelerated VIPS is required
• Experience with Vplan/Testplan development and development of verification environment from ground up is good
• Experience in common communication protocols such as AMBA,I2C, SPI,UART and Ethernet is an added advantage
• Should be able to communicate technical details very effectively with both customers (product line teams) and peers
• Good debugging and analytical skills