Senior Digital Implementation Engineer

• STA flow setup, convergence, reviews
• Timing constraint development, analysis, validation and debug
• Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner
• STA flow optimization
• Work on design automation using TCL/Perl/Python

Position Requirements:

• BTech/MTech degree in Electrical/Electronics with 2-10 years of experience
• Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below).
• Ability to develop complex timing constraints by working with designers.
• Should have experience in IP/subsystem/full-chip timing constraints
• Knowledge of timing commands and constructs supported across synthesis, STA and PD tools
• Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation
• Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure
• Sound understanding of Scan/DFT modes and timing
• Familiar with digital flow design aspects RTL to GDS
• Proficiency in tcl/perl/python scripts and automation on timing analysis tools
• Innovate on the flows to resolve timing or DRC issues
• Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage.
• Good communication skills in cross-collaborative environment