Senior Design Verification Engineer

• 3rd party, industry-standard simulator productivity improvements and breakthrough innovations, integration into ADI DV solutions and creating differentiating solutions
• Evaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and quality
• Consulting design teams on verification best practices and approaches and providing the right solutions
• Training, deployment, and support of verification methodologies within ADI
• Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future

Job Requirements:

• BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes
• Strong hands-on experience in Cadence/Synopsys simulation and debug tools like Xcelium/VCS, vManager, Verisium, Verdi or similar is required
• Expertise in automation and scripting languages like Perl, Python, and shell scripting
• Proficient knowledge in DV methodologies like GLS, Coverage
• Proficient in Version control systems, such as Perforce, SVN, SOS
• Proficient in Verilog, System Verilog and UVM
• Ability to manage multiple tasks and work effectively in a fast-paced environment
• Able to communicate effectively
• Good debugging and analytical skills.