QU

RTL Design - Sr Staff Engineer

Qualcomm
Chennai15-20 LPA Posted 20 Jun 2025
FULL TIME
Design Compiler
primetime
RTL
SOC design
Timing Closure

Job Description

  • 15+ years of experience in SoC design
  • Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC.
  • Understanding of Memory controller designs and microprocessors is an added advantage
  • Hands on experience in constraint development and timing closure
  • Work closely with the SoC verification and validation teams for pre/post Silicon debug
  • Hands on experience in Low power SoC design is required
  • Experience in Synthesis / Understanding of timing concepts for ASIC is required.
  • Hands on experience in Multi Clock designs, Asynchronous interface is a must.
  • Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

OR

Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.

OR

PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

  • 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering
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