RTL Design Engineer

Expertise and strong hands-on experience in RTL design using System Verilog or VHDL

Digital system architecture, Processor subsystem architecture and block definition

Experience working on complex SoCs

RTL design quality analysis – Lint, CDC, RDC

Good understanding of digital design Synthesis, DFT and Static Timing Analysis

Basic understanding of mixed-signal designs

Experience with gate level simulations and debug

Experience in digital verification is a plus

Strong written and verbal communication skills