R&D Engineering, Staff Engineer

• Responsible for functional verification involving coherent and non-coherent IP designs.
• Collaborating with market leaders in High Performance Computing, Data Centre, Mobile/Client, Automotive, and IoT segments to define and develop products that meet complex verification requirements.
• Architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
• Developing verification plans and driving functional coverage-driven verification closure of real designs.
• Debugging and resolving issues in verification environments to ensure robust and reliable verification processes.

The Impact You Will Have:

• Enhancing the reliability and performance of high-performance computing and data center systems through rigorous verification processes.
• Contributing to the advancement of mobile and client devices by ensuring the integrity and functionality of their verification protocols.
• Driving innovation in the automotive sector by developing robust verification solutions for automotive systems.
• Supporting the growth of IoT applications by providing reliable and efficient verification for IoT devices.
• Collaborating with industry leaders to shape the future of system verification and contribute to technological advancements.
• Ensuring the successful implementation and integration of verification IPs, thereby enhancing the overall quality of our products.

What You'll Need:

• B.E/B.Tech in Electrical Engineering/Electronics & Communications Engineering with 5-8 years of relevant experience, OR M.E/M.Tech in VLSI Design/Microelectronics with 4-8 years of relevant experience.
• Hands-on experience in architecting and building SystemVerilog UVM-based verification components, testbenches, checkers, scoreboards, and verification IPs.
• In-depth understanding of cache coherency protocols such as Protocol experience: Should have experience in any of the protocols, UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol.
• Experience in creating verification plans and achieving functional coverage-driven verification closure of real designs.
• Proficiency in writing scripts using Perl, Python, and Shell scripting.