Define and implement comprehensive verification strategies for complex ASIC designs.
Develop robust unit and SoC level test benches using UVM, ensuring thorough design validation.
Apply expertise in various aspects of digital verification, including constrained random verification, functional and code coverage, assertion methodologies, and formal verification.
Drive behavioral modeling of analog blocks, SystemVerilog Real-Number Modeling, behavioral model validation, and utilize mixed-signal simulators like Cadence Xcelium.
Engage with processor-based designs, ensuring their robust verification.
Implement and manage the Gate Level Simulation (GLS) verification flow for comprehensive SoC verification.
Collaborate effectively with peers, managers, and project stakeholders, communicating clearly both verbally and in writing.

Required Qualifications:

Bachelor's or Master's degree in Engineering (Electronic Engineering) or equivalent.
15 years of ASIC design verification or related work experience.
Demonstrated leadership skills in defining and implementing verification strategies.
Proficiency in developing unit and SoC level test benches using UVM.
Skilled in constrained random verification, functional coverage, code coverage, assertion methodology, and formal verification.
Experience in behavioral modeling of analog blocks, SystemVerilog Real-Number Modeling, behavioral model validation, and mixed-signal simulators (e.g., Cadence Xcelium).
Experience working with processors.
Proficiency in Gate Level Simulation (GLS) verification flow for SoC verification.
Strong command of Verilog, C/C++, SystemC, Java, and scripting languages (TCL/Perl/Python/shell-scripting).
Excellent interpersonal and communication skills, coupled with a desire to take on diverse challenges.
Self-motivated and enthusiastic.

Desirable Skills:

Experience in Property Specification Language (PSL).
Proficiency in MATLAB (including for co-simulation and HDL generation) and digital signal processing.
Knowledge of low-power methodologies such as CPF/UPF.