SO

Physical Design Engineer

Bangalore ₹6-8 LPA Posted 2 Sept 2025

FULL TIME

Sta

Dft

RTL

Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR).
Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges.
Proficient with industry-standard tools: Cadence Innovus, Synopsys ICC2, and scripting in Tcl, Perl, Python for automation and flow development.
Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe.
Collaborate cross-functionally with RTL, STA, DFT, verification, and packaging teams to ensure smooth integration and closure.
Manage comprehensive signoff processes, including STA (PrimeTime SI), EM/IR analysis (RedHawk), and physical verification (Calibre); handle ECOs and DRC/LVS clean-up.
Provide technical leadership, mentor junior engineers, and contribute to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm