MS Design Verification Engineer

• B.Tech/M.Tech with 8+ years of industry experience in analog/mixed signal behavioral modeling at various levels of abstraction and full chip verification (AMS and DMS DV)
• Good understanding of analog design concepts and mixed signal design architectures. Exposure to products that integrate a wide variety of analog/mixed-signal building blocks such as power management, ADCs, DACs, PLL, bandgap references, oscillators etc and related digital control and signal processing
• Demonstrated experience of verification plan, verification environment development and verification/debug of complex mixed signal products at chip-top level
• Experience of co-simulations with analog model/transistor level and digital RTL/Gate+SDFs, experience of circuit simulations with Spice/Fast Spice simulators
• Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe

Responsibilities

• Come up with verification strategy for a product after going through product requirements and design specifications
• Interact with digital/analog leads to get agreement on verification strategy
• Create models for analog/mixed-signal blocks for chip-top verification, tradeoff accuracy Vs speed. Validate models against actual design (self-checking tests)
• Create verification plans, build verification environment, develop self-checking testcases. Bring up chip top mixed-signal verification environments (AMS and DMS DV environments)
• Deploy industry standard SV/UVM based metric driven verification approach
• Collaborate and work closely with team members from various disciplines (system architects, digital design, analog design, digital DV etc) for first pass silicon
• Support test and characterization teams in post-silicon validation
• Collaborate with CAD team to deploy next generation innovative design verification methodologies to reduce overall TTM, mentor junior DV engineers in the team