CA

Lead Product Engineer

Cadence Design Systems
Bangalore3-11 LPA Posted 9 Jun 2025
FULL TIME
Dft
ATPG
Timing Closure

Job Description

Skill Required:

  • Be a part of the Modus PE team in identifying new features in DFT ATPG domains and developing product spec for implementation.
  • Work with RD PV teams with validation of said features, Development of methodologies, flows and documentation to help improve usability and quality of the tool
  • Collaborate with field to benchmark on customer designs towards successful deployment
  • Work with RD teams to drive and influence the development of new tools, as well as the modification of existing tools to address the needs of customers and market.
  • Support existing Innovus hierarchical partition tools and top-level timing closure flow.
  • Support benchmarks and solve complex customer hierarchical issues.

Educational Qualification:

  • B. E/BTech/ME/MTech. in EE/ECE/CS

Required Skills