CA

Lead Analog Design Engineer

Cadence Design Systems
Bangalore3-11 LPA Posted 12 Jun 2025
FULL TIME
Silicon Validation

Job Description

Design and lead high speed IP (USB3, PCIE, DPHY etc) development. Need to be a strong individual contributor in analog domain. Will be required to participate in all aspects of development - analog design, layout, digital design, documentation and silicon validation. Would be required to participate in customer facing discussions.

Requirements

  • B. Tech/BE/ME/Mtech
  • Exp - 4 +yrs
  • Hands on design experience in various analog IP like PLLs, data converters, serial interfaces etc.
  • Must have participated in full cycles of analog IP creation - right from spec to silicon debug and char
  • Must have good communication skills and should be team player.
  • Working experience in PHY (PCIE, USB2, USB3) development is desired

Required Skills

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