QUQualcomm
Display Design Verification - Sr Staff Engineer
Chennai ₹6-11 LPA Posted 20 Jun 2025
FULL TIME
Soc Architecture
System Verilog
Verilog
Uvm
Python
Job Description
- Strong knowledge of digital design and SOC architecture.
- Good understanding of OOP concepts.
- Experience in HVL such as System Verilog, UVM/OVM & System C.
- Experience in HDL such as Verilog.
- Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia.
- Familiarity with Power-aware Verification, GLS, Test vector generation is a plus.
- Exposure to Version managers like Clearcase/Perforce.
- Scripting language like Perl, Tcl or Python.
- Analytical and Debugging skills.
- Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus.
Minimum Qualifications:
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
- 12-15 years of experience with a Bachelor's/Master's degree in Electrical/Electronics engineering.