Digital Design Verification Engineer

• Knowledge with test plan and testbench infrastructure development
• Knowledge with the typical verification cycle in IC design flow
• Proficiency in programming

Education and Experience

• BS or MS Electronics, Electrical or Computer Engineering with 0-3 years of related experience

Additional Qualifications

• Knowledge in Verilog/System Verilog
• Knowledge in Python, PERL, and Shell scripting
• Knowledge with Universal Verification Methodology (UVM), and Object-Oriented Programming (OOP)