Design Engineering Architech

Key Responsibilities:

• Architect RTL and physical design strategies aligning with product requirements and performance goals.
• Oversee synthesis, timing closure, and verification activities ensuring design robustness.
• Define and improve ASIC design flows including verification and sign-off methodologies.
• Mentor and lead engineering teams to adopt best practices and achieve project milestones.
• Collaborate with cross-functional teams including verification, physical design, and product engineering to deliver quality silicon on schedule.

Educational Qualification:

• Bachelor's or Master's degree in Electrical/Electronics/VLSI Engineering or related field.
• 10+ years of experience in ASIC/SoC design with strong leadership and architectural skills.