ASIC Power Management Architect, Silicon

Responsibilities

• Define ASIC power management architecture details for an ASIC that includes functions such as image compute, CPU/GPU, for maximum performance under power and thermal constraints.
• Prototype and validate for the next generation SoC power management system applicable at different design levels.
• Analyze implementation and models, and test the performance of power management solutions.
• Produce detailed documentation for the proposed implementation of power management schemes. Produce detailed trade-off analysis for engineering reviews and product roadmap decisions.
• Collaborate with software and the power architecture team to build system level designs and methods.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 5 years of experience in power management or post-silicon measurements and validation.
• 3 years of experience with power management validation.

Preferred qualifications:

• Master's degree or PhD in Electronics, Computer Engineering or Computer Science, with an emphasis on computer architecture and performance and power analysis.
• Knowledge of Dynamic Voltage Frequency Scaling (DVFS), idle power management, and system mitigation.
• Knowledge of the impact of software and architectural design decisions on power and thermal behavior of the system, such as thermal mitigation and scheduling, and cross-layer policy design.