CY

AMS Verification Engineer

Cyient Inc
Hyderabad3-12 LPA Posted 20 Jun 2025
FULL TIME
universal verification methodology
Linux Shell Scripting
Perl Scripts
Verilog

Job Description

  • BE/B.Tech in ECE /M.Tech in VLSI with 0 to 2 years experience in Analog Mixed Signal Verification
  • Good academic score
  • Verilog knowledge is a plus
  • Good communication and documentation skills

the candidate must have the above skills mentioned

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